1. Field of Invention
The present invention relates to a method of fabricating a thin film transistor, more particularly, to a method of fabricating a lightly-doped drain (xe2x80x9cLDDxe2x80x9d) thin film transistor of a coplanar type wherein the transistor has an LDD region of uniform resistance formed by locating a peak point of dopant in an active layer covered with an insulating layer wherein the dopant is very lightly distributed.
2. Description of Related Art
Compared to an amorphous silicon Thin Film Transistor (xe2x80x9cTFTxe2x80x9d), a polycrystalline silicon TFT has a higher mobility of electrons or holes which enables the latter to embody a complementary thin film transistor, namely a complementary metal oxide silicon thin film transistor (xe2x80x9cCMOS TFTxe2x80x9d). The development of laser crystallization enables the fabrication of polycrystalline silicon transistors on a large scale glass substrate at a normal temperature of fabricating amorphous silicon Thin Film Transistors (xe2x80x9cTFTxe2x80x9d).
A liquid crystal display (xe2x80x9cLCDxe2x80x9d) using polycrystalline silicon TFTs includes both a driver and a pixel array on a glass substrate. TFTs in the driver carry out fast switching operations due to the characteristic advantages of polycrystalline silicon, thus minimizing problems. However, TFTs for switching pixels in the pixel array decrease the image characteristics since the voltage width of a pixel electrode is broadened due to a large drain current during off-state. Conventionally, a lightly doped drain or an offset structure is applied to a TFT in order to properly reduce the off current in a pixel array.
FIGS. 1A-1D show schematic cross-sectional views of one related art method for fabricating an LDD TFT.
Referring to FIG. 1A, a buffer layer 10 is formed on an insulated substrate 100. An active layer 11 is defined by a photolithographic process, which is a patterning process common to all TFT fabrication processes, involving the patterning of a polycrystalline silicon layer formed on the buffer layer 10. The polycrystalline silicon layer may be formed by depositing amorphous silicon on the buffer layer 10 and by crystallizing the amorphous silicon with dehydrogenation and a laser annealing process. Subsequently, an insulating layer 12L and a conductive layer 13L are respectively formed on disclosed surfaces of the buffer layer 10 and the active layer 11.
As shown in FIG. 1B, a gate electrode 13 is formed by etching the conductive layer 13L with photolithography. A gate insulating layer 12 is formed by etching the insulating layer 12L using the gate electrode 13 as an etch mask.
According to FIG. 1C, a photoresist pattern PR blocks both the gate electrode 13 and the active layer 11 and an LDD region is formed in the active layer 11. A source region 11S and a drain region 11D are formed in the active layer 11 by doping the whole surface of the substrate 100 heavily with n-type impurities.
Referring to FIG. 1D, after the photoresist pattern PR has been removed, an LDD region 11L is formed in the active layer 11 by lightly doping the whole surface of the substrate with the n-type impurities. Thereafter, the n-type impurities are activated and the following processes are carried out.
In the above-described related art, the insulating layer covering the active layer is etched as shown in FIG. 1B in order to form a gate insulating layer. Generally, the step of etching the insulating layer is carried out by a dry etch. The dry etch removes the etched layer after having reacted with plasma to be volatile in a vacuum chamber.
However, when the insulating layer is etched according to the prior art method, a surface of the active layer is exposed during the etching process. Consequently, the exposed portion of the active layer is damaged by the plasma, thereby reducing the desirable characteristics of a TFT such as decreased on-current and an increased off-current effects
FIGS. 2A-2D show schematic cross-sectional views of another method of fabricating an LDD TFT. These figures show how to form an LDD region by utilizing a Gaussian distribution of impurity density.
As illustrated in FIG. 2A, an active layer 21 is formed on a buffer layer 20 which has been formed on an insulated substrate 200. The active layer maybe formed by depositing an amorphous silicon layer on the buffer layer 20, by forming a polycrystalline silicon layer by crystallizing the amorphous silicon layer and subsequently, by patterning the polycrystalline silicon layer with photolithography.
A gate insulating layer 22L is formed on the buffer layer 20 and the active layer 21. Thereafter, a conductive layer 23L is deposited on the gate insulating layer 22L. A gate electrode 23 is formed by etching the conductive layer 23L with photolithography.
Referring to FIG. 2B, the substrate 200 is heavily doped with impurities so that the insulating layer 22L includes the maximum value of impurity density and the active layer 21 has a certain density distribution corresponding to a tail region in accordance with a Gaussian distribution. Accordingly, the active layer 21 becomes lightly doped with n-type impurities, which is achieved by controlling the implantation energy of impurities which locates the maximum value of density.
Referring to FIG. 2C, a gate insulating layer 22 is formed by patterning the insulating layer 22L with photolithography. In this case, the gate insulating layer 22 is defined to be extended out of the gate electrode 23 in order to cover an LDD region in the active layer 21.
Referring to FIG. 2D, a source region 21S and a drain region 21D are formed on portions of the active layer 21 which are heavily doped with n-type impurities in use of the gate insulating layer 22 as a dopant-blocking mask. In this case, a part blocked from the heavy doping in the active layer 21 where impurities are lightly distributed becomes an LDD region 21L. Then, following processes including activation are carried out.
In the above description, when a heavy doping step is being processed, the LDD region is formed by locating the maximum value of impurity density at the insulating layer 22L and by placing a certain density distribution corresponding to a tail region at the active layer 21 in accordance with a Gaussian distribution. However, as the slope of the density distribution near the tail region becomes steep, the density of the impurities distributed in the active layer is influenced by the variation of the thickness of the insulating layer. Generally, the insulating layer is deposited within an error of approximately 100xe2x96xa1, thereby causing a corresponding error in the LDD region between tens of Kxe2x96xa1 and several Mxe2x96xa1. Accordingly, the effect of the TFT is reduced since the resistance is not maintained uniformly in the LDD region.
Moreover, a laser may break down the insulating layer as the substrate is irradiated with a laser of high energy in order to activate an LDD region in the active layer having been lightly doped with impurities.
Accordingly, the present invention is directed to a method of fabricating a thin film transistor that substantially obviates one or more of the problems due to limitations and disadvantages of the prior art.
The object of the present invention is to provide a method of fabricating a thin film transistor which has an LDD region of uniform resistance formed by locating a peak point of dopant in an active layer covered with an insulating layer wherein the dopant is very lightly distributed.
Another object of the present invention is to provide a method of fabricating a thin film transistor having an LDD region of uniform resistance attained by decreasing the density variation of impurities which are distributed very lightly.
Additional features and advantages of the invention will become apparent from the following detailed description of the present invention. The objectives and other advantages of the invention will be obtained by the structures described in the written description and claims hereof as well as the appended drawings.
In order to achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes the steps of forming an active layer on an insulated substrate, forming an insulating layer covering the active layer, forming a gate electrode on the insulating layer over the active layer, lightly doping the active layer as a target with impurities, forming a gate insulating layer by patterning the insulating layer to be extended out of the gate electrode, and forming a source region and a drain region in portions of the active layer exposed by the step of forming the gate insulating layer, wherein the impurities have a density of under 0.1% in a source gas for doping and are composed of PH3 values of under 0.1% and H2 over 99.9%.
The foregoing general description and the following detailed descriptions are exemplary and explanatory in nature and are intended to provide further descriptions and explanation of the invention as claimed.